1. Field
Embodiments of the invention relate to the field of a patch mechanism, and more specifically, to a system and method that can be used to detect and workaround defects and conditions existing in an integrated circuit chip.
2. Background
Typically, host processor communicates with various end-devices, such as hard drives, USB (Universal Serial Bus) devices and PCI (Peripheral Component Interconnect) add-on cards, via a chipset. The chipset may include one or more integrated circuit chips, such as a memory controller and an I/O (input/output) controller. As an integrated circuit chip, such as the I/O controller, is tested, errors or defects may be discovered in the chip. Conventionally, when an error or defect is detected in the integrated circuit, one of a number of approaches may be taken. One approach is to de-feature the functionality if possible. This approach reduces the value of the product and may often be unacceptable. Another approach is to workaround the problem through software settings if possible. In this approach, the BIOS modifies the hardware behavior as the system boots to avoid the problem in the future. However, the software settings that are currently available tend to be very specific and, therefore, typically not useful for complex defects in highly integrated silicon chip. A further approach is to workaround the problem through modified software algorithms if possible. This approach can impact performance greatly and is not available in many situations.
In computer systems, host processor generates request cycles, which are directed towards the end-devices. Generally, there are two categories of cycles, i.e. a write request cycle that is used to transport data from the host processor to the end-user device or a read request cycle that is used to read data from the end-user device. When a read request cycle is targeting a specific device, a successful read request would result in read data being returned as a completion packet to the requesting device, such as the processor. However, if there is a design error in the decode logic of the end-device, this may cause the read request targeting it to be ignored. In such situations, a completion packet will not be returned to the processor that issued the read request and this may cause the processor to hang or freeze. Such problem may arise in situations, for example, where the cycle type accepted by a decode logic of the end-device is incorrect with respect to the specification. Conventionally, a hardware bug such as this may be fixed through changes made to the silicon design once the bug has been localized in the design. This approach, however, tends to be very expensive and requires long throughput to make the fix available.